Digital encoder apparatus

ABSTRACT

A matrix of switches is arranged in columns and rows with separate column and row conductors coupling, in parallel, all the switches of the respectively associated column and row. A closed switch selects one column conductor and one row conductor, the opposite ends of each of which are serially coupled to a number of input windings that are associated with a like number of transformers. Each transformer is assigned a respectively associated binary value whereby the closing of a switch concurrently induces in the associated output windings output signals that are representative of the associated binary value.

United States Patent lnventor George T. Osborne St. Paul, Minn.

Appl. No. 846,121

Filed July 30, 1969 Patented Apr. 6, 1971 Assignee Sperry RandCorporation New York, N.Y.

DIGITAL ENCODER APPARATUS 3 Claims, 2 Drawing Figs.

US. Cl 340/365, 178/17R, 235/145R, 340/166R Int. Cl G06f 3/02 Field ofSearch 340/166, 337, 365, 354; 178/17, 79; 235/145, 146

References Cited UNITED STATES PATENTS 3,284,773 11/1966 Say Kay 340/1473,317,896 5/1967 Bollesenetal 3,441,671 4/1969 Hennig ABSTRACT: A matrixof switches is arranged in columns and rows with separate column and rowconductors coupling, in parallel, all the switches of the respectivelyassociated column and row. A closed switch selects one column conductorand one row conductor, the opposite ends of each of which are seriallycoupled to a number of input windings that are associated with a likenumber of transformers. Each transformer is assigned a respectivelyassociated binary value whereby the closing of a switch concurrentlyinduces in the associated output windings output signals that arerepresentative of the associated binary value.

I l I l PATENTED APR 6197! 'SHEET 1 or 2 E N w Y B WWJ T N N 7 NY W T W6M. R w 6 Fig. la

"PATENTEU APR 6 I97! sum 2 0F 2 INVENTOR GEORGE T. 0530 ATTORNEY DIGITALENCODER APPARATUS BACKGROUND OF THE INVENTION keyboard key to anassociated binary code. Such digital,en-'

coder is utilized in its preferred embodiment to replace a core ropememory system that utilizes saturable cores as the memory devices. Suchcore rope memory systems are well known in the art with the followingarticles providing an excellent background therefor: Applications ofRope Memory Devices," Computer Design, Aug. 1964, pages l222; Core-RopeMemory, Computer Design, Jun. 1963, pages 16- 19.

Such prior art rope memories utilize saturable transformer elements suchas ferrite toroidal cores as the memory elements with such cores beingestablished in a first or a second and opposite polarizationrepresentative of the storage of a l or of a 0, as is well known in theart. Such saturable transfonner arrangements require circuitry variouslycalled inhibit, set, or reset filed whereby the saturable transformerelements may be set into their desired magnetic polarizationrepresentative of the stored data. See the J. AQRajChman US. Pat. No.2,734,182. The use of nonsaturable transformer elements as the memoryelements eliminates many of the onerous requirements of core ropememories utilizing saturable transformer elements as the memory devices.In the use of nonsaturable transformer elements the elements do notrequire a predeter- 3Q mined state of magnetic polarization, suchelements having no magnetic remanence; the stored data beingrepresentative of the threading or nonthreading of the memory element bythe word line being sufficient to provide a pulse or no-pulse on a senseline coupled to the associated nonsaturable transformer element.

Such prior art core rope memories, which are in essence digitalencoders, utilize a plurality of word lines, one word line for each wordassociated with the read-only memory and a plurality of sense lines, onesense line associated with each of the memory elements of the array. Itis desirable, in operator keyboard units, where each key on the keyboardincorporates a switch for selecting one of the multibit words of thedigital encoder, to reduce to a minimum the number of wires that couplethe switches in the keyboard to the associated memory elements, such asthe transformers utilized by the present invention. It is thus an objectof the present invention to provide an improved digital encoder for anoperators keyboard unit providing a reduced number of conductorsintercoupling the keyboard switches and the related transformerelements.

SUMMARY OF THE INVENTION The present invention relates to a digitalencoder in which the closing of a single switch produces, in-parallel,all the bits of a multibit word. In the preferred embodiment, theswitches are integral with associated keys of an operator's keyboardunit, and are electrically arranged in a matrix array of rows andcolumns. Separate row and column conductors couple, in parallel, all theswitches of the respectively associated row and column whereby theselecting, or depressing, of a single key selects, or energizes, the onerespectively associated row conductor, column conductor combination. Therow and column conductors are, in turn, coupled to input windings ofselected ones of a plurality of transformers, one input winding perselected transformer. Each transformer is assigned a respectivelyassociated binary value, i.e., weighted, whereby the closing of a singleswitch concurrently produces at the output windings of the selectedtransformers a plurality of weighted binary signals that arerepresentative of the digital value of the associated key.

, BRIEF. DESCRIPTION OFTI-IE DRAWING DESCRIPTION OF THE PREFERREDEMBODIMENT With particular reference to the single FIGURE there ispresented an illustration of the electrical schematic of the encoder ofthe present invention. Encoder I0 essentially consists of switch array12 and transformer array 14 electrically intercoupled by row conductors16 and column conductors 18. The arrangement is such that the closing ofa single switch selects, or energizes, one row conductor 16, column con-10 ductor 18 combination whereby transformer array 14 is caused to emitfrom the respectively selected transformer output windings weightedbinary signals that are representative of the digital value of theassociated key 20.

Switch array 12 is comprised of 64 switches 20 arranged in an 8 X8matrix array of rows and columns. Separate row and column conductorscouple, in parallel, all the switches 20 of tee respectively associatedrow and column. As an example, the closing of switch 20a selects, byelectrically intercoupling, row conductor 16a and column conductor l8e.

Transformer array 14 is comprised of 12 transformers C10, C11, C12, C00,C01, C02, R03, R04, R05, R13, R14, R15 each having a single outputwinding and one or more input windings. The l2transfonners are dividedinto groups of six transformers; a group R associated with the eight rowconductors l6; and a group C associated with the eight column conductors18. Each row conductor 16 and each column conductor 18 is coupled tothree serially associated input windings, each of the seriallyassociated input windings being associated with a separate associatedtransformer, of three of the six transformers of the associated group.Each transformer is assigned a digital (positional) weight, 2", and abinary value, 0 or 1, as noted in Table A.

TABLE A GROUP R GROUP C XME R Weight Value XME R Weight Value 20 11 3 2|n 2 n 22 no 25 n 20 '1 W 111" 21 11 1/ 4 I1 1! 22 Ill/I 25 n Operationof the single illustrated embodiment is best discussed with respect tothe effects produced by the closing of a single switch 20, such as bythe depressing of the single associated keyboard key. In the illustratedarray of 2 switches 20 arranged in 2" rows and 2" columns, each of the2" row conductors 16 and each of the 2' column conductors 18 is coupledto 2'-l serially coupled input windings of the 2 (2" l) transformersthat are associated with the row or column conductors. Thus, the closingof one switch 20, through node 32 and the serially aligned capacitor C,resistor R and voltage source E on one end and the grounded terminal onthe other end, causes a current signal to flow through the selected, orenergized, one row-conductor, column-conductor combination inducing inthe single output windings of the affected 2 (2"1) transformers, signalsthat are assigned respective digital weights and binary values. Thesesignals are, in turn, through suitable amplifying devices A coupled torespectively associated inputs of the flip-flop stages 2, 2 -2"' of aholding register 30. These concurrently generated output signals arerepresentative of the bits of the 2 bit word that is associated with theparticular depressed key that closes the associated switch 20 of switcharray 12.

As an example of the above, the closing of switch 20a energizes rowconductor 16a and column conductor 16:: through voltage source E. Rowconductor 16a is coupled to the following serially coupled inputwindings of the associated transformers: ROS-1, R04-2, R03-1: columnconductor l8e is coupled to the following serially coupled inputwindings of the as sociated transformers: 012-1, COL-2, C00-1. Using themultibitword of the form 2, 2, -2 where bit 2 is the lowest ordered bitand bit 2 is the highest orderedbit, themultibit output word is 001000.

The multibit half-word byte associated with each row conductor 16 andeach column conductor 18 is placed alongside the respectively associatedconductor for ease in evaluating the multibit word that is associatedwith each switch 20 at the intersection of the associated row conductor,column conductor combination. Thus, it can be seen that the closing ofswitch 20b couples to register 20 the multibit word 101011 while theclosing of switch 200 couples to register 30 the multibit word 0101 10.

Although the illustrated embodiment includes both 1 and transformers,e.g., transformers C and C00, the 0 transformers C00, C01, C02, R03,R04, R05 may be dispensed with where no output 0 signal is required,such as where register 30 is initially set to all 0s with only 1 signalsrequired to set the associated stages of register 30. However, thisconfiguration does permit uneven loading of the row conductors 16 andthe column conductors 18 whereby variations in the output signal inputsto the associated amplifiers A may be undesirable.

lclaim:

1. Encoder apparatus, comprising:

a plurality of switching means arranged in rows and columns;

a plurality of row conductors, each parallel coupling only the switchingmeans of an associated row;

a plurality of column conductors, each parallel coupling only theswitching means of an associated column;

a plurality of row transformers, each having a single output winding andat least one input winding;

a plurality of column transformers, each having a single output windingand at least one input winding;

means separately coupling each of the row conductors to only one inputwinding of selected ones of said row transformers;

means separately coupling each of the column conductors to only oneinput winding of selected ones of said column transformers;

means for causing a current signal to flow through the selected rowconductor, column conductor combination when one of said switching meansis closed; and

said selected row-conductor, column-conductor combination inducingoutput signals in the output windings of the selected row transformersand column transformers, said output signals representative of amultibit word associated with the closed switching means.

2. Encoder apparatus, comprising:

2" switching means arranged in 2" rows and 2" columns;

2" row conductors each parallel coupling only the switching means of anassociated row;

2" column conductors each parallel coupling only the switching means ofan associated column;

n row transformers, each having a single output winding and 2, 2', ...2"input windings, respectively;

n column transformers, each having a single output winding and 2, 2, 2""input windings, respectively;

means separately serially coupling each of the 2" row conductors to onlyone input winding of selected ones of said row transformers;

means separately coupling each of the 2" column conductors to only oneinput winding of selected ones of said column transformers;

means for causing a current signal to flow through the selectedrow-conductor, column-conductor combination when one of said switchingmeans is closed; and

said selected row-conductor, column-conductor combination inducingoutput signals in the output windings of the selected row transformersand column transformers, said output signals representative of a 2' bitword associated with the closed switching means.

3. Encoder apparatus, comprising:

2" switching means arranged in 2" rows and 2" columns;

2" row conductors, each parallel coupling only the switching means of anassociated row;

2" column conductors, each parallel coupling only the switching means ofan associated column; n 0 row transformers, each having a single outputwinding and 2, 2, 2" input windings, respectively;

n 1 row transformers, each having a single output winding and 2, 2', 2""input windings, respectively;

n 0 column transformers, each having a single output winding and 2, 2',2" input windings, respectively;

n 1 column transformers, each having a single output winding and 2, 2',2 input windings, respectively;

means separately serially coupling each of the 2" row conductors to onlyone input winding of n alternative ones of said 0 or 1 row transformers;

means separately serially coupling each of the 2" column conductors toonly one input winding of n alternative ones of said 0 or 1 columntransformers;

means for causing a current signal to flow through the selectedrow-conductor, column-conductor combination when one of said switchingmeans is closed; and

said selected row-conductor, column-conductor combination inducingoutput signals in the output windings of the selected row transformersand column transformers, said output signal representative of a 2' bitword associated with the closed switching means.

UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent No. 3 573807 Dated p 1 6 197] George T. Osborne Inventor(s) It is certified thaterror appears in the above-identified patent and that said LettersPatent are hereby corrected as shown below:

Column 3 line 41 and Column 4 lines 16 42 and 44 "row-conductor,column-conductor", each occurrence, should r row conductor, columnconductor. Column 4, lines 4, 6, 28

30, 32 and 34,

2I111 should read 2 Column 4, lines 27, 31, 37 and 40, "0'', eachoccurrence, sho read "O" same column 4, lines 29, 33 and 40, "l", eacoccurrence, should read "1" Signed and sealed this 7th day of December1971.

[SEAL] Attest:

EDWARD M. FLETCHER,JR. ROBERT GOTTSCHALK Attesting Officer ActingCommissioner of Pat FORM PO 1050(10-69)

1. Encoder apparatus, comprising: a plurality of switching meansarranged in rows and columns; a plurality of row conductors, eachparallel coupling only the switching means of an associated row; aplurality of column conductors, each parallel coupling only theswitching means of an associated column; a plurality of rowtransformers, each having a single output winding and at least one inputwinding; a plurality of column transformers, each having a single outputwinding and at least one input winding; means separately coupling eachof the row conductors to only one input winding of selected ones of saidrow transformers; means separately coupling each of the columnconductors to only one input winding of selected ones of said columntransformers; means for causing a current signal to flow through theselected row conductor, column conductor combination when one of saidswitching means is closed; and said selected row-conductor,column-conductor combination inducing output signals in the outputwindings of the selected row transformers and column transformers, saidoutput signals representative of a multibit word associated with theclosed switching means.
 2. Encoder apparatus, comprising: 22n switchingmeans arranged in 2n rows and 2n columns; 2n row conductors eachparallel coupling only the switching means of an associated row; 2ncolumn conductors each parallel coupling only the switching means of anassociated column; n row transformers, each having a single outputwinding and 20, 21, ... 2n 1 input windings, respectively; n columntransformers, each having a single output winding and 20, 21, ... 2n 1input windings, respectively; means separately serially coupling each ofthe 2n row conductors to only one input winding of selected ones of saidrow transformers; means separately coupling each of the 2n columnconductors to only one input winding of selected ones of said columntransformers; means for causing a current signal to flow through theselected row-conductor, column-conductor combination when one of saidswitching means is closed; and said selected row-conductor,column-conductor combination inducing output signals in the outputwindings of the selected row transformers and column transformers, saidoutput signals representative of a 2n bit word associated with theclosed switching means.
 3. Encoder apparatus, comprising: 22n switchingmeans arranged in 2n rows and 2n columns; 2n row conductors, eachparallel coupling only the switching means of an associated row; 2ncolumn conductors, each parallel coupling only the switching means of anassociated column; n 0 row transformers, each having a single outputwinding and 20, 21, ... 2n 1 input windings, respectively; n 1 rowtransformers, each having a single output winding and 20, 21, ... 2n 1input windings, respectively; n 0 column transformers, each having asingle output winding and 20, 21, ... 2n 1 input windings, respectively;n 1 column transformers, each having a single output winding and 20, 21,... 2n 1 input windings, respectively; means separately seriallycoupling each of the 2n row conductors to only one input winding of nalternative ones of said 0 or 1 row transformers; means separatelyserially coupling each of the 2n column conductors to only one inputwinding of n alternative ones of said 0 or 1 column transformers; meansfor causing a current signal to flow through the selected row-conductor,column-conductor combination when one of said switching means is closed;and said selected row-conductor, column-conductor combination inducingoutput signals in the output windings of the selected row transformersand column transformers, said output signal representative of a 2n bitword associated with the closed switching means.